Mohamed Bouaziz

Using the MLIR infrastructure to analyse and optimize the architectural design of dataflow architectures targeting the FPGA platforms.

Addressing the problem of Acceleration of FPGA Routing using Parallelism. To maintain the scalability of deterministic routers, a divide-and-conquer approach was explored to build on top of VTR 8 by analysing different configurations of load balancing between parallel routers and identifying their trade-offs in terms of determinism, memory bounding, and computation bounding and their implications on scalability. The best configuration demonstrated 2.4X speedup on eight threads in a shared-memory multi-threaded environment.

Extending Autovesk auto-vectoriser to allow cross-compilation on various architectures using Multi-Level Intermediate Representation (MLIR).